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KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 68 of 120 Ver. 0.9 KS152JB2
would be one interframe space period after the line is sensed as being idle.
As the number of stations approach 256 the probability of a successful transmission decreases
rapidly. If there are more than 256 stations involved in the collision there would be no resolution
since at least two of the stations will always have the same backoff interval selected.
All the stations monitor the link as long as that station is active, even if not attempting to transmit.
This is to ensure that each station always defers the minimum amount of time before attempting a
transmission and so that addresses are recognized. However, the collision detect circuitry operates
slightly differently.
In normal back-off mode, a transmitting station always monitors the link while transmitting. If a
collision is detected one or more of the transmitting stations apply the jam signal and all transmit-
ting stations enter the back-off algorithm. The receiving stations also constantly monitor for a col-
lision but do not take part in the resolution phase. This allows a station to try to transmit in the
middle of a resolution period. This in turn may or may not cause another collision. If the new sta-
tion trying to transmit on the link does so during an unused slot time then there will probably not
be a collision. If trying to transmit during a used slot time, then there will probably be a collision.
The actions the receiver does take when detecting a collision is to just stop receiving data if data
has not been loaded into RFIFO or to stop reception, clear receiver enable (REN) and set the
receiver abort flag (RCABT - RSTAT.6).
If deterministic resolution is used, the transmitting stations go through pretty much the same pro-
cess as in normal back-off, except that the slots are predetermined. All the receivers go through
the back-off algorithm and may only transmit during their assigned slot.
3.6.4 SUCCESSFUL ENDING OF TRANSMISSIONS AND RECEPTIONS
In both CSMA/CD and SDLC modes, the TDN bit is set and TEN cleared at the end of a success-
ful transmission. The end of the transmission occurs when the TFIFO is empty and the last byte
has been transmitted. In CSMA/CD the user should clear the TCDCNT register after successful
transmission.
At the end of a successful reception, the RDN bit is set and GREN is cleared. The end of reception
occurs when the EOF flag is detected by the GSC hardware.
3.7 GSC Register Descriptions
ADR0,1,2,3 (95H, 0A5H, 0B5H, 0C5H) - Address Match Registers 0,1,2,3 - Contains the address
match values which determines which data will be accepted as valid. In 8 bit addressing mode, a
match with any of the four registers will trigger acceptance. In 16 bit addressing mode a match
with ADR1:ADR0 or ADR3:ADR2 will be accepted. Addressing mode is determined in
GMOD(AL).
AMSK0,1 (0D5H, 0E5H) - Address Mask 0,1 - Identifies which bits in ADR0,1 are “don’t care”