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KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 76 of 120 Ver. 0.9 KS152JB2
4.0 DMA Operation
The C152 contains DMA (Direct Memory Accessing) logic to perform high speed data transfers
between any two of
Internal Data RAM
Internal SFRs
External Data RAM
In external RAM is involved, the Port 2 and Port 0 pins are used as the address/data bus, and
RD
and
WR signals are generated as required.
Hardware is also implemented to generate a Hold Request signal and await a Hold Acknowledge
response before commencing a DMA that involves external RAM.
Alternatively, The Hold/Hold Acknowledge hardware can be programed to accept a Hold Request
signal from an external device and generate a Hold Acknowledge signal in response, to indicate to
the requesting device that the C152 will not commence a DMA to or from external RAM while
the Hold Request is active.
4.1 DMA with the 80C152
The C152 contains two identical general purpose 8-it DMA channels with 16-bit address ability:
DMA0 and DAM1. DMA transfers can be executed by either channel independent of the other,
but only by one channel at a time. During the time that a DMA transfer is being executed, pro-
gram execution is suspended. A DMA transfer takes one machine cycle (12 oscillator periods) per
byte transferred, except when the destination and source are both in External Data RAM. In that
case the transfer takes two machine cycles per byte. The term DMA Cycle will be used to mean
the transfer of a single data byte, whether it takes 1 or 2 machine cycles.
Associated with each channel are seven SFRs, shown below SARLn and SARHn holds the low
and high bytes of the source address. Taken together they form a 16-bit Source Address Register.
DARLn and DARHn hold the low and high bytes of the destination address, and together form the
Destination Address Register. BCRLn and BCRHn hold the low and high bytes of the number of
bytes to be transferred, and together form the Byte Count Register. DCONn contains control and
flag bits.