Filter
Top Products
KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 90 of 120 Ver. 0.9 KS152JB2
decides it wants to do Burst mode DMA. The sequence of events might be:
Instruction cycle (sets GO bit in DCON1)
Instruction cycle (during which TFNF gets set)
DMA0 cycle
DMA1 cycle
DMA1 cycle
DMA1 cycle
......
DMA1 cycle (completes channel 1 burst)
Instruction cycle
DMA0 cycle
Instruction cycle
...........
This sequence begins with two Instruction cycles. The first one accesses a DMA register
(DCON1), and therefore is followed by another Instruction cycle, which presumably does not
access a DMA register. After the second Instruction cycle both channels are ready to generate
DMA cycles, and channel 0 of course takes precedence. After the DM0 cycle, channel 0 must
wait for an Instruction cycle before it can access TFIFO again. Channel 1, being in Burst mode,
doesn’t have that restriction, and is therefore granted a DMA1 cycle. After the first DMA1 cycle,
channel 0 is still waiting for an Instruction cycle and channel 1 still does not have that restriction.
There follows another DMA1 cycle.
The result is that in this particular case channel 0 has to wait until channel 1 completes its Burst
mode DMA, and then has to wait for an Instruction cycle to be generated, before it can continue
its own DMA to TFIFO. The delay in servicing TFFIO can cause an Underflow condition in the
GSC transmission.
The delay will not occur if channel 1 is configured to Alternate Cycles mode, since channel 0
would then see the Instruction cycles it needs to complete its logic requirements for asserting its
request.
4.4.1 DMA Arbitration with Hold/Hold Ack
The Hold/Hold Acknowledge feature is invoked by setting either the ARB or REQ bit in PCON.
Their effect is to add the requirements of the Hold/Hold Ack protocol to mode_logic ( ). This
amounts to replacing every expression “return 1” in with the expression “return hld_hlda_logic (
) “, where hld_hlda_logic ( ) is a function which returns 1 if the Hold/Hold Ack protocol is satis-
fied, and returns 0 otherwise. A suitable definition for hld_hlda_logic () is shown in Figure 4.14.