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Chapter 5 Hardware Functional Descriptions 5-7
5.2.1.1 Electronic Fuse
The Electronic Fuse (Efuse) block within the UltraSPARC T2 processor contains
configuration information that is electronically burned in manufacturing.
UltraSPARC T2
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
SPARC
core
L2
Bank 0
L2
Bank 1
L2
Bank 0
L2
Bank 1
L2
Bank 0
L2
Bank 1
L2
Bank 0
L2
Bank 1
Cache
Crossbar
(CCX)
TCU CCU Efuse
10 Gb MAC
10 Gb MAC
NIU
SIU
PCI-E
SSI ROM I/F
1.2
GHz
667
MHz
4.0
GHz
64
128
64
64
128
64
64
128
64
64
128
64
MCU0
MCU1
MCU2
MCU3
Fully buffered
DIMMs (FBD)
10
14
10
14
10
14
10
14
10
14
10
14
10
14
10
14
Optional dual channel mode