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5-18 Netra CP3260 Blade Server User’s Guide • April 2009
A reset mask register is provided in the FPGA to allow the masking of resets to
individual I/O components. For example, a PEX_RESET_L reset from the
UltraSPARC T2 processor resets only those I/O subcomponents not masked by the
reset mask register.
5.2.10 ATCA Power Module (−48V to 12V)
The Netra CP3260 blade server uses the Artesyn ATCA power module solution. The
Artesyn power module provides an integrated ATCA power solution that meets
PICMG 3.0 requirements, including dual bus input, DC isolation, hold up, hot-plug,
and management power (3.3V standby). It provides a 12V intermediate bus as
backend power. Some of the salient features of the module are:
■ 210 watts output power.
■ Input-to-output isolation.
■ 12V with current rating of 17.5A.
■ 3.3V standby at 1.82A. (The IPMC draws power from IPMI Power (3.3V_STBY) so
it can remain functional even if back-end logic is powered down.)
■ Isolated remote ON/OFF.
■ Isolated “A” and “B” bus detect signals.
■ High efficiency, typically 88 percent.
■ Operating input voltage: −39V to −72V.
■ The I
2
C interface monitors the status of fuse, input voltages, output voltages, and
temperature and sends an alarm if any of the parameters are outside the
programmable threshold.
■ FRU information.
5.2.11 TOD Clock Battery
The TOD clock battery must be type CR1632, with a minimum of 4ma abnormal
charging current rating (for example; a Renata CR1632).
Caution – Risk of explosion if battery is replaced by an incorrect type.
Dispose of batteries properly in accordance with manufacturer’s instructions and
local regulations.
See Section 2.5.3, “Adding or Replacing TOD Clock Battery” on page 2-14 for battery
location and installation instructions.