Filter
Top Products
www.ti.com
5.1.2VideoPortPeripheralControlRegister(PCR)
GPIORegisters
Thevideoportperipheralcontrolregister(PCR)determinesoperationduringemulation.
Normaloperationistonothalttheportduringemulationsuspend.Thisallowsadisplayedimagetoremain
visibleduringsuspend.However,thiswillonlyworkifoneofthecontinuouscapture/displaymodesis
selectedbecausenon-continuousmodesrequireCPUinterventionforEDMAstocontinueindefinitely(and
theCPUishaltedduringemulationsuspend).
WhenFREE=0,emulationsuspendcanoccur.Clocksandcounterscontinuetoruninordertomaintain
synchronizationwithexternaldevices.ThevideoportwaitsuntilafieldboundarytohaltEDMAevent
generation,sothatuponrestartthevideoportcanbegingeneratingeventsagainattheprecisepointitleft
off.Afterexitingsuspend,thevideoportwaitsforthecorrectfieldboundarytooccurandthenreenables
EDMAevents.TheEDMApointerswillbeatthecorrectlocationforcapture/displaytoresumewhereitleft
off.TheemulationsuspendoperationissimilartotheBLKCAPorBLKDISPoperationwiththedifference
beingthatBLKCAPandBLKDISPoperationstakeeffectimmediatelyratherthanatfieldcompletionand
relyonyoutoresettheEDMAmechanismbeforetheyarecleared.
Thereisnoseparateemulationsuspendmechanismonthevideocaptureside.Thefieldandframe
operation(seeTable3-6)canbeusedasemulationsuspend.
Thevideoportperipheralcontrolregister(PCR)isshowninFigure5-2anddescribedinTable5-3.
Figure5-2.VideoPortPeripheralControlRegister(PCR)
3116
Reserved
R-0
153210
ReservedPERENSOFTFREE
R-0R/W-0R-0R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-3.VideoPortPeripheralControlRegister(PCR)FieldDescriptions
Bitfield
(1)
symval
(1)
ValueDescription
31-3Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfield
hasnoeffect.
2PERENOF(value)Peripheralenablebit.
DEFAULT0Videoportisdisabled.Portclock(VCLK1,VCLK2,STCLK)inputsaregatedoffto
savepower.EDMAaccesstothevideoportisstillacknowledgedbutindeterminate
DISABLE
readdataisreturnedandwritedataisdiscarded.
ENABLE1Videoportisenabled.
1SOFTOF(value)Softbitenablemodebit.ThisbitisusedinconjunctionwithFREEbittodetermine
stateofvideoportclockduringemulationsuspend.ThisbithasnoeffectifFREE=1.
DEFAULT0Thecurrentfieldiscompleteduponemulationsuspend.Aftercompletion,nonew
EDMAeventsaregenerated.Theportclocksandcounterscontinuetoruninorderto
STOP
maintainsynchronization.Nointerruptsaregenerated.Iftheportisindisplaymode,
videocontrolsignalscontinuetobeoutputandthedefaultdatavalueisoutputduring
theactivevideowindow.
COMP1Isnotdefinedforthisperipheral;thebitishardwiredto0.
0FREEOF(value)Free-runningenablemodebit.ThisbitisusedinconjunctionwithSOFTbitto
determinestateofvideoportduringemulationsuspend.
SOFT0Free-runningmodeisdisabled.Duringemulationsuspend,SOFTbitdetermines
operationofvideoport.
DEFAULT1Free-runningmodeisenabled.Videoportignorestheemulationsuspendsignaland
continuestofunctionasnormal.
(1)
ForCSLimplementation,usethenotationVP_PCR_field_symval
SPRUEM1–May2007General-PurposeI/OOperation153
SubmitDocumentationFeedback