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5.1.8VideoPortPinDataClearRegister(PDCLR)
GPIORegisters
PDCLRisanaliasofthevideoportpindataoutputregister(PDOUT)forwritesonlyandprovidesan
alternatemeansofdrivingGPIOoutputslow.Writinga1toabitofPDCLRclearsthecorrespondingbitin
PDOUT.Writinga0hasnoeffect.Registerreadsreturnall0s.
Thevideoportpindataclearregister(PDCLR)isshowninFigure5-8anddescribedinTable5-9.
Figure5-8.VideoPortPinDataClearRegister(PDCLR)
3124
Reserved
R-0
2322212019181716
ReservedPDCLR22PDCLR21PDCLR20PDCLR19PDCLR18PDCLR17PDCLR16
R-0W-0W-0W-0W-0W-0W-0W-0
15141312111098
PDCLR15PDCLR14PDCLR13PDCLR12ReservedReservedPDCLR9PDCLR8
W-0W-0W-0W-0W-0W-0W-0W-0
76543210
PDCLR7PDCLR6PDCLR5PDCLR4PDCLR3PDCLR2ReservedReserved
W-0W-0W-0W-0W-0W-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-9.VideoPortPinDataClearRegister(PDCLR)FieldDescriptions
Bitfield
(1)
symval
(1)
ValueDescription
31-23Reserved-0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfield
hasnoeffect.
22PDCLR22OF(value)AllowsPDOUT22bittobeclearedtoalogiclowwithoutaffectingotherI/Opins
controlledbythesameport.
DEFAULT0Noeffect.
NONE
VCTL3CLR1ClearsPDOUT22(VCTL3)bitto0.
21PDCLR21OF(value)AllowsPDOUT21bittobeclearedtoalogiclowwithoutaffectingotherI/Opins
controlledbythesameport.
DEFAULT0Noeffect.
NONE
VCTL2CLR1ClearsPDOUT21(VCTL2)bitto0.
20PDCLR20OF(value)AllowsPDOUT20bittobeclearedtoalogiclowwithoutaffectingotherI/Opins
controlledbythesameport.
DEFAULT0Noeffect.
NONE
VCTL1CLR1ClearsPDOUT20(VCTL1)bitto0.
19-2PDCLR[19-2]OF(value)AllowsPDOUT[19-2]bittobeclearedtoalogiclowwithoutaffectingotherI/Opins
controlledbythesameport.
DEFAULT0Noeffect.
NONE
VDATAnCLR1ClearsPDOUT[n](VDATA[n])bitto0.
(1)
ForCSLimplementation,usethenotationVP_PDCLR_PDCLRn_symval
General-PurposeI/OOperation 162SPRUEM1–May2007
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