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6.1Overview
22kΩ
100pF
5VDC
2.2kΩ
0.1
mF
VCXO
27MHz
VDAC
VIC
STCLK
VDATA[7−0](TSIdatain)
VCLK1(TSIclock)
VCTL1(CAPENA)
VCTL2(PACSTRT)
VCTL3(PACERR)
Satellite/
cable
decoder
with
FEC
Video
port A
DSP
6.2Interface
Overview
TheVCXOinterpolatedcontrol(VIC)portprovidessingle-bitinterpolatedVCXOcontrolwithresolution
from9bitstoupto16bits.Thefrequencyofinterpolationisdependentontheresolutionneeded.
Whenthevideoportisusedintransportstreaminterface(TCI)mode,theVICportisusedtocontrolthe
systemclock,VCXO,forMPEGtransportstream(Figure6-1).
TheVICportsupportsfollowingfeatures:
•Single-bitinterpolatedVCXOcontrol
•Programmableprecisionfrom9to16bits
Figure6-1.TCISystemBlockDiagram
ThepinlistforVICportisshowninTable6-1(pinsare3.3VI/Os).
Table6-1.VICPortInterfaceSignals
VICPortSignalDirectionDescription
VDACOutputVCXOcontrol
STCLKInputSystemtimeclock
VCXOInterpolatedControlPort 168SPRUEM1–May2007
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