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6.3OperationalDetails
R + kf
k u (
3
Ǹ
(p
2
(2
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2
)ń3)
OperationalDetails
Synchronizationisanimportantaspectofdecodingandpresentingdatainreal-timedigitaldatadelivery
systems.ThisisaddressedintheMPEGtransportpacketsbytransmittingtiminginformationinthe
adaptationfieldsofselecteddatapackets.Thisservesasareferencefortimingcomparisoninthe
receivingsystem.Asampleofthe27-MHzclock,theprogramclockreference(PCR)headerisshownin
Figure6-2,istransmittedwithinthebitstream,whichindicatestheexpectedtimeatthecompletionof
readingthefieldfromthebitstreamatthetransportdecoder.Thesampleisa42-bitfield,9bitscyclefrom
0to299at27MHz,whiletheother33-bitfieldisincrementedby1eachtimethe9-bitfieldreachesa
valueof299.Thetransportdatapacketsareinsyncwiththeserversystemclock.
Figure6-2.ProgramClockReference(PCR)HeaderFormat
471514980
PCRReservedPCRextension
ThevideoportinconjunctionwiththeVICportusesacombinedhardwareandsoftwaresolutionto
synchronizethetransportsystemtimeclock(STC)withtheclockreferencetransmittedinthebitstream.
Thevideoportmaintainsahardwarecounterthatcountsthesystemtime.Thecounterisdrivenbysystem
timeclock(STCLK)inputdrivenbyanexternalVCXO,controlledbytheVICport.
Onreceptionofapacket,thevideoportcapturesasnapshotofthecounter.Softwareusesthistimestamp
todeterminethedeviationofthesystemtimeclockfromtheserverclock,anddrivesVCTLoutputofthe
VICporttokeepitsynchronized.
AnytimeapacketwithaPCRisreceived,thetimestampforthatpacketiscomparedwiththePCRvalue
insoftware.APLLisimplementedinsoftwaretosynchronizetheSTCLKwiththesystemtimeclock.The
DSPupdatestheVICinputregister(VICIN)usingtheoutputfromthisalgorithm,whichinturndrivesthe
VCTLoutputthatcontrolsthesystemtimeclockVCXO.
IffisthefrequencyofPCRsintheincomingbitstream,theinterpolationrateRoftheVCTLoutputisgiven
inEquation6-1,wherekisdeterminedbytheprecisionβspecifiedbyyou.
Equation6-1.RelationshipBetweenInterpolationRateandInputFrequency
Equation6-2givestherelationbetweenkandtheprecisionβ.
Equation6-2.RelationshipofFrequencyMultipliertoPrecision
Table6-2givessomekandRvaluesfordifferentβ'swithffixedat40kHz.Onceasuitableinterpolation
frequencyisdetermined,theclockdividercanbeset.
Table6-2.ExampleValuesforInterpolationRate
βkR
996.03.8MHz
10151.06.0MHz
11240.09.6MHz
12381.015.2MHz
13605.024.2MHz
14960.038.4MHz
151523.060.9MHz
162418.096.7MHz
SPRUEM1–May2007VCXOInterpolatedControlPort169
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