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4.1.3SyncSignalGeneration
4.1.4ExternalSyncOperation
4.1.5PortSyncOperation
Video port 0
display
Can sync to
Video port 1
display
Can sync to
Video port 2
display
4.2BT.656VideoDisplayMode
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4
VDOUT[9−2]
VCLKOUT
BT.656VideoDisplayMode
Thevideodisplaymodulemustgenerateanumberofcontrolsignalsforbothinternalandexternaluse.As
seeninSection4.1.2,theHSYNC,HBLNK,VSYNC,VBLNK,andFLDsignalsaregenerateddirectlyfrom
thepixelandlinecountersandcomparisonregisters.Severaladditionalsignalsarealsogenerated
indirectlyforuseinexternalcontrol.
Acompositeblank(CBLNK)signalisgeneratedasthelogical-ORoftheHBLNKandVBLNKsignals.A
compositesync(CSYNC)signalisalsogeneratedasthelogical-ORoftheHSYNCandVSYNCsignals.
(ThisisnotatrueanalogCSYNC,whichmustincludeserrationpulsesduringVSYNCandequalization
pulsesduringverticalfrontandbackporchperiods.)Finally,anactivevideo(AVID)signalisgenerated.
AVIDistheinvertedCBLNKsignalindicatingwhenactivevideodataisbeingoutput.
UptothreeoftheeightsyncsignalsmaybeoutputonVCTL1,VCTL2,andVCTL3asselectedbythe
videodisplaycontrolregister(VDCTL).Eachsignalmaybeoutputinitsnon-invertedorinvertedform,as
selectedbytheVCTnPbitsinthevideoportcontrolregister(VPCTL).
Thevideodisplaymodulemaybesynchronizedwithanexternalvideosourceusingexternalsyncsignals.
VCTL1maybeconfiguredasanexternalhorizontalsyncinput.WhentheexternalHSYNCisasserted,
FPCOUNTisloadedwiththeHRLDvalueandVCCOUNTisloadedwiththeCRLDvalue.VCTL2maybe
configuredasanexternalverticalsyncinput.WhentheexternalVSYNCisassertedduringfield1,
FLCOUNTisloadedwiththeVRLDvalue.FielddeterminationismadeusingeitherVCTL3asanexternal
FLDinputorbyfielddetectlogicusingtheVSYNCandHSYNCinputs.
Thevideodisplaymodulemaybesynchronizedwiththevideodisplaymoduleofanothervideoportonthe
device.Thismodeisprovidedtoenabletheoutputof24-bitRGBdata(forexample,8bitsofRand8bits
ofGonvideoport0operatingindual-channelsynched8-bitrawmode,and8bitsofBonvideoport1
operatingin8-bitrawmodewithVP1synchedtoVP0.)TheslaveportmusthavethesameVCLKINand
programmedregistervaluesasthemasterport.Themasterportprovidesthecontrolsignalsnecessaryto
resettheslaveportcounterssothattheymaintainsynchronization.Eachvideoportmayonlysynchronize
tothepreviousvideoport(theonewithalowernumber).Anexampleforathreeportdeviceisshownin
Figure4-7.
Figure4-7.VideoDisplayModuleSynchronizationChain
TheBT.656displaymodeoutputs8-bit4:2:2co-sitedlumaandchromadatamultiplexedintoasingledata
stream.Pixelsareoutputinpairswitheachpairconsistingoftwolumasamplesandtwochromasamples.
Thechromasamplesareassociatedwiththefirstlumapixelofthepair.Outputpixelsarevalidonthe
positiveedgeofVCLKOUTinthesequenceCbYCrYasshowninFigure4-8.
Figure4-8.BT.656OutputSequence
98VideoDisplayPortSPRUEM1–May2007
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