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2.1ResetOperation
2.1.1Power-OnReset
2.1.2PeripheralBusReset
2.1.3SoftwarePortReset
ResetOperation
Thevideoporthasseveralsourcesandtypesofresets.Theactionsperformedbytheseresetsandthe
stateoftheportfollowingtheresetsisdescribedinthefollowingsections.
Power-onresetisanasynchronoushardwareresetcausedbyachip-levelresetoperation.Theresetis
initiatedbyapower-onresetinputtothevideoport.Whentheinputisactive,theportplacesallI/Os
(VD[19-2],VCTL1,VCTL2,VCTL3,andVCLK1)inahigh-impedancestate.
Peripheralbusresetisasynchronoushardwareresetcausedbyachip-levelresetoperation.Theresetis
initiatedbyaperipheralbusresetinputtothevideoport.Thisresetcanbeusedinternally(continuously
asserted)todisablethevideoportforlow-poweroperation.Whentheinputisactive,theportdoesthe
following:
•Places(keeps)allI/Os(VD[19-2],VCTL1,VCTL2,VCTL3,andVCLK1)inahigh-impedancestate.
•FlushestheFIFOs(resetspointers)
•Resetsallport,capture,display,andGPIOregisterstotheirdefaultvalues.Thesemaynotcomplete
untiltheappropriatemoduleclock(VCLK1,STCLK)edgesoccurtosynchronouslyreleasethelogic
fromreset.
•ClearsPERENbitinPCRto0.
•SetsVPHLTbitinVPCTLto1.
Whiletheperipheralremainsdisabled(PEREN=0):
•VCLK1,VCLK2,andSTCLKaregatedofftosaveperipheralpower.
•Peripheralbusaccessesareacknowledged(RREADY/WREADYreturned)topreventEDMAlock-up.
(Anyvaluereturnedonreads,dataacceptedordiscardedonwrites.)
•PeripheralbusMMRinterfaceallowsaccesstoGPIOregistersonly(PID,PCR,PFUNC,PDIR,PIN,
PDOUT,PDSET,PDCLR,PIEN,PIPOL,PISTAT,andPICLR).
•PortI/Os(VD[19-2],VCTL1,VCTL2,VCTL3,andVCLK2)remaininahigh-impedancestateunless
enabledasGPIObythePFUNCbits.
IfsoftwaresetsthePERENbitinPCRbuttheVPHLTbitinVPCTLremainsset:
•VCLK1,VCLK2,andSTCLKareenabledtotheport(allowinglogicresettocomplete).
•Peripheralbusaccessesareacknowledged(RREADY/WREADYreturned)topreventEDMAlock-up.
(Anyvaluereturnedonreads,dataacceptedordiscardedonwrites.)
•PeripheralbusMMRinterfaceallowsaccesstoallregisters.
•PortI/Os(VD[19-2],VCTL1,VCTL2,VCTL3,andVCLK2)remaininahigh-impedancestateunless
enabledasGPIObythePFUNCbits.
•VPCTLbitsmaybeset(untiltheVPHLTbitiscleared).
AsoftwareportresetmaybeperformedontheentirevideoportbysettingtheVPRSTbitinVPCTL.This
behavesidenticallytotheperipheralbusresetexceptthatitdoesnotclearthePERENbitinPCR.This
reset:
•Performsaresetonallportlogic(channellogicmaystayinresetuntilportinputclockpulsesoccur).
•Self-clearstheVPRSTbitto0butleavestheVPHLTbitset.TheVCLK1inputmustbeclockingin
orderforthisresettotakeeffect.
30VideoPortSPRUEM1–May2007
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