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5.1.10VideoPortPinInterruptPolarityRegister(PIPOL)
GPIORegisters
ThePIPOLdeterminestheGPIOpinsignalpolaritythatgeneratesaninterrupt.
Thevideoportpininterruptpolarityregister(PIPOL)isshowninFigure5-10anddescribedinTable5-11.
Figure5-10.VideoPortPinInterruptPolarityRegister(PIPOL)
3124
Reserved
R-0
2322212019181716
ReservedPIPOL22PIPOL21PIPOL20PIPOL19PIPOL18PIPOL17PIPOL16
R-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
15141312111098
PIPOL15PIPOL14PIPOL13PIPOL12ReservedReservedPIPOL9PIPOL8
R/W-0R/W-0R/W-0R/W-0R-0R-0R/W-0R/W-0
76543210
PIPOL7PIPOL6PIPOL5PIPOL4PIPOL3PIPOL2ReservedReserved
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-11.VideoPortPinInterruptPolarityRegister(PIPOL)FieldDescriptions
Bitfield
(1)
symval
(1)
ValueDescription
31-23Reserved-0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfield
hasnoeffect.
22PIPOL22OF(value)PIPOL22bitdeterminestheVCTL3pinsignalpolaritythatgeneratesaninterrupt.
DEFAULT0Interruptiscausedbyalow-to-hightransitionontheVCTL3pin.
VCTL3ACTHI
VCTL3ACTLO1Interruptiscausedbyahigh-to-lowtransitionontheVCTL3pin.
21PIPOL21OF(value)PIPOL21bitdeterminestheVCTL2pinsignalpolaritythatgeneratesaninterrupt.
DEFAULT0Interruptiscausedbyalow-to-hightransitionontheVCTL2pin.
VCTL2ACTHI
VCTL2ACTLO1Interruptiscausedbyahigh-to-lowtransitionontheVCTL2pin.
20PIPOL20OF(value)PIPOL20bitdeterminestheVCTL1pinsignalpolaritythatgeneratesaninterrupt.
DEFAULT0Interruptiscausedbyalow-to-hightransitionontheVCTL1pin.
VCTL1ACTHI
VCTL1ACTLO1Interruptiscausedbyahigh-to-lowtransitionontheVCTL1pin.
19-2PIPOL[19-2]OF(value)PIPOL[19-2]bitdeterminesthecorrespondingVDATA[n]pinsignalpolaritythat
generatesaninterrupt.
DEFAULT0Interruptiscausedbyalow-to-hightransitionontheVDATA[n]pin.
VDATAnACTHI
VDATAnACTLO1Interruptiscausedbyahigh-to-lowtransitionontheVDATA[n]pin.
(1)
ForCSLimplementation,usethenotationVP_PIPOL_PIPOLn_symval.
General-PurposeI/OOperation 164SPRUEM1–May2007
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