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5.1.7VideoPortPinDataSetRegister(PDSET)
GPIORegisters
PDSETisanaliasofthevideoportpindataoutputregister(PDOUT)forwritesonlyandprovidesan
alternatemeansofdrivingGPIOoutputshigh.Writinga1toabitofPDSETsetsthecorrespondingbitin
PDOUT.Writinga0hasnoeffect.Registerreadsreturnall0s.
Thevideoportpindatasetregister(PDSET)isshowninFigure5-7anddescribedinTable5-8.
Figure5-7.VideoPortPinDataSetRegister(PDSET)
3124
Reserved
R-0
2322212019181716
ReservedPDSET22PDSET21PDSET20PDSET19PDSET18PDSET17PDSET16
R-0W-0W-0W-0W-0W-0W-0W-0
15141312111098
PDSET15PDSET14PDSET13PDSET12ReservedReservedPDSET9PDSET8
W-0W-0W-0W-0R-0R-0W-0W-0
76543210
PDSET7PDSET6PDSET5PDSET4PDSET3PDSET2ReservedReserved
W-0W-0W-0W-0W-0W-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-8.VideoPortPinDataSetRegister(PDSET)FieldDescriptions
Bitfield
(1)
symval
(1)
ValueDescription
31-23Reserved-0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfield
hasnoeffect.
22PDSET22OF(value)AllowsPDOUT22bittobesettoalogichighwithoutaffectingotherI/Opinscontrolled
bythesameport.
DEFAULT0Noeffect.
NONE
VCTL3HI1SetsPDOUT22(VCTL3)bitto1.
21PDSET21OF(value)AllowsPDOUT21bittobesettoalogichighwithoutaffectingotherI/Opinscontrolled
bythesameport.
DEFAULT0Noeffect.
NONE
VCTL2HI1SetsPDOUT21(VCTL2)bitto1.
20PDSET20OF(value)AllowsPDOUT20bittobesettoalogichighwithoutaffectingotherI/Opinscontrolled
bythesameport.
DEFAULT0Noeffect.
NONE
VCTL1HI1SetsPDOUT20(VCTL1)bitto1.
19-2PDSET[19-2]OF(value)AllowsPDOUT[19-2]bittobesettoalogichighwithoutaffectingotherI/Opins
controlledbythesameport.
DEFAULT0Noeffect.
NONE
VDATAnHI1SetsPDOUT[n](VDATA[n])bitto1.
(1)
ForCSLimplementation,usethenotationVP_PDSET_PDSETn_symval
SPRUEM1–May2007General-PurposeI/OOperation161
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