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5.1.9VideoPortPinInterruptEnableRegister(PIEN)
GPIORegisters
TheGPIOscanbeusedtogenerateDSPinterruptsorEDMAevents.ThePIENselectswhichpinsmay
beusedtogenerateaninterrupt.OnlypinswhosecorrespondingbitsinPIENaresetmaycausetheir
correspondingPISTATbittobeset.
InterruptsareenabledonaGPIOpinwhenthecorrespondingbitinPIENisset,thepinisenabledfor
GPIOinPFUNC,andthepinisconfiguredasaninputinPDIR.
Thevideoportpininterruptenableregister(PIEN)isshowninFigure5-9anddescribedinTable5-10.
Figure5-9.VideoPortPinInterruptEnableRegister(PIEN)
3124
Reserved
R-0
2322212019181716
ReservedPIEN22PIEN21PIEN20PIEN19PIEN18PIEN17PIEN16
R-0W-0W-0W-0W-0W-0W-0W-0
15141312111098
PIEN15PIEN14PIEN13PIEN12ReservedReservedPIEN9PIEN8
W-0W-0W-0W-0R-0R-0W-0W-0
76543210
PIEN7PIEN6PIEN5PIEN4PIEN3PIEN2ReservedReserved
W-0W-0W-0W-0W-0W-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-10.VideoPortPinInterruptEnableRegister(PIEN)FieldDescriptions
Bitfield
(1)
symval
(1)
ValueDescription
31-23Reserved-0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfield
hasnoeffect.
22PIEN22OF(value)PIEN22bitenablestheinterruptontheVCTL3pin.
DEFAULT0Interruptisdisabled.
VCTL3LO
VCTL3HI1Pinenablestheinterrupt.
21PIEN21OF(value)PIEN21bitenablestheinterruptontheVCTL2pin.
DEFAULT0Interruptisdisabled.
VCTL2LO
VCTL2HI1Pinenablestheinterrupt.
20PIEN20OF(value)PIEN20bitenablestheinterruptontheVCTL1pin.
DEFAULT0Interruptisdisabled.
VCTL1LO
VCTL1HI1Pinenablestheinterrupt.
19-2PIEN[19-2]OF(value)PIEN[19-2]bitsenabletheinterruptonthecorrespondingVDATA[n]pin.
DEFAULT0Interruptisdisabled.
VDATAnLO
VDATAnHI1Pinnenablestheinterrupt.
(1)
ForCSLimplementation,usethenotationVP_PIEN_PIENn_symval
SPRUEM1–May2007General-PurposeI/OOperation163
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