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quad-rank DIMMs in the sockets with white release tabs and dual-rank DIMMs in the sockets with
black release tabs.
• In a dual- or four-processor configuration, the memory configuration for each processor must be
identical. For example, if you populate socket A1 for processor 1, then you must populate socket B1
for processor 2, and so on.
• Memory modules of different sizes can be mixed provided that other memory population rules are
followed (for example, 8 GB and 16 GB memory modules can be mixed).
• Populate four DIMMs per processor (one DIMM per channel) at a time to maximize performance.
• If memory modules with different speeds are installed, they operate at the speed of the slowest
installed memory module(s) or slower depending on system DIMM configuration.
• Populate DIMMs based on the following processor-heat sink configurations.
Table 1. Heat sink — processor configurations
Processor
configuration
Processor type (in
Watts)
Heat
sink
width
Number of DIMMs
Maximum system
capacity
Reliability, Availability,
and Serviceability (RAS)
features
Dual processor Up to 105 W, 120 W,
or 135 W
74
mm
24 24
Quad processor Up to 105 W, 120 W,
or 135 W
74
mm
48 48
NOTE: If you are using a 1.8 inch hard drive/SSD system with four processors,
ensure that you use only 74 mm wide heat sinks for processors up to 105 W,
120 W, or 135 W.
Up to 120 W or 135 W 94
mm
40 (Three DIMMs in
channel 0 and channel
2 and two DIMMs in
channel 1 and channel
3)
32 (Two DIMMs per
channel)
NOTE: If you are using a 2.5 inch hard drive/SSD system with four processors,
ensure that you use only 94 mm wide heat sinks for processors up to 120 W or
135 W.
Mode-specific guidelines
Four memory channels are allocated to each processor. The possible configurations depend on the
memory mode selected.
NOTE: x4 and x8 DRAM based DIMMs can be mixed providing support for RAS features. However,
all guidelines for specific RAS features must be followed. x4 DRAM based DIMMs retain Single
Device Data Correction (SDDC) in memory optimized (independent channel) mode. x8 DRAM based
DIMMs require Advanced ECC mode to gain SDDC.
The following sections provide additional slot population guidelines for each mode.
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