Intel CM8062101038606 Computer Hardware User Manual


 
Electrical Specifications
158 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
7.1.9.3.5 SVID Power State Functions: SetPS
The processor has three power state functions and these will be set seamlessly via the
SVID bus using the SetPS command. Based on the power state command, the SetPS
commands sends information to VR controller to configure the VR to improve efficiency,
especially at light loads. For example, typical power states are:
PS0(00h): Represents full power or active mode
PS1(01h): Represents a light load 5 A to 20 A
PS2(02h): Represents a very light load <5 A
The VR may change its configuration to meet the processor’s power needs with greater
efficiency. For example, it may reduce the number of active phases, transition from
CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode,
reduce the switching frequency or pulse skip, or change to asynchronous regulation.
For example, typical power states are 00h = run in normal mode; a command of 01h=
shed phases mode, and an 02h=pulse skip.
The VR may reduce the number of active phases from PS0 to PS1 or PS0 to PS2 for
example. There are multiple VR design schemes that can be used to maintain a greater
efficiency in these different power states, please work with your VR controller suppliers
for optimizations.
The SetPS command sends a byte that is encoded as to what power state the VR
should transition to.
If a power state is not supported by the controller, the slave should acknowledge with
command rejected (11b)
Note the mapping of power states 0-n will be detailed in the
VR12/IMVP7 Pulse Width
Modulation Specification.
If the VR is in a low power state and receives a SetVID command moving the VID up
then the VR exits the low power state to normal mode (PS0) to move the voltage up as
fast as possible. The processor must re-issue low power state (PS1 or PS2) command if
it is in a low current condition at the new higher voltage. See Figure 7-2 for VR power
state transitions.
Figure 7-2. VR Power-State Transitions
PS0
PS2PS1