Intel CM8062101038606 Computer Hardware User Manual


 
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families 17
Datasheet Volume One
Overview
x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1.
x8 port (Port 1) may negotiate down to x4, x2, or x1.
x4 port (Port 0) may negotiate down to x2, or x1.
When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported.
Non-Transparent Bridge (NTB) is supported by PCIe* Port3a/IOU1. For more details
on NTB mode operation refer to PCI Express Base Specification - Revision 3.0:
x4 or x8 widths and at PCIe* 1.0, 2.0, 3.0 speeds
Two usage models; NTB attached to a Root Port or NTB attached to another
NTB
Supports three 64-bit BARs
Supports posted writes and non-posted memory read transactions across the
NTB
Supports INTx, MSI and MSI-X mechanisms for interrupts on both side of NTB
in upstream direction only
Address Translation Services (ATS) 1.0 support
Hierarchical PCI-compliant configuration mechanism for downstream devices.
Traditional PCI style traffic (asynchronous snooped, PCI ordering).
PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Automatic discovery, negotiation, and training of link out of reset.
Supports receiving and decoding 64 bits of address from PCI Express*.
Memory transactions received from PCI Express* that go above the top of
physical address space (when Intel VT-d is enabled, the check would be against
the translated HPA (Host Physical Address) address) are reported as errors by
the processor.
Outbound access to PCI Express* will always have address bits 63 to 46
cleared.
Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
Power Management Event (PME) functions.
Message Signaled Interrupt (MSI and MSI-X) messages
Degraded Mode support and Lane Reversal support
Static lane numbering reversal and polarity inversion support