Intel CM8062101038606 Computer Hardware User Manual


 
Overview
16 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
UDIMMs x8, x16
RDIMMs x4, x8
LRDIMM x4, x8 (2-Gb and 4-Gb only)
Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical
zeros with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS), native 1 and 2 socket
platforms - Intel® Xeon® processor E5-1600 and E5-2600 product families only
Minimum memory configuration: independent channel support with 1 DIMM
populated
Integrated dual SMBus master controllers
Command launch modes of 1n/2n
RAS Support (including and not limited to):
Rank Level Sparing and Device Tagging
Demand and Patrol Scrubbing
DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device failure. Independent channel mode supports x4 SDDC. x8 SDDC
requires lockstep mode
Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in
lockstep mode
The combination of memory channel pair lockstep and memory mirroring is not
supported
Data scrambling with address to ease detection of write errors to an incorrect
address.
Error reporting via Machine Check Architecture
Read Retry during CRC error handling checks by iMC
Channel mirroring within a socket Channel Mirroring mode is supported on
memory channels 0 & 1 and channels 2 & 3
Corrupt Data Containment
—MCA Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature via two memory
signals, MEM_HOT_C{01/23}_N
1.2.2 PCI Express*
The PCI Express* port(s) are fully-compliant to the PCI Express* Base
Specification, Revision 3.0 (PCIe* 3.0)
Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)
Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express*
devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports
4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0),
also can be downgraded to x2 or x1
Negotiating down to narrower widths is supported, see Figure 1-3: