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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
31
3.1.7 Multiple Processor Initialization
IA-32 processors have a microcode-based Boot Strap Processor (BSP) arbitration protocol. On
reset, all of the processors compete to become the BSP. If a serious error is detected during a
Built-in Self-Test (BIST), that processor does not participate in the initialization protocol. A single
processor that successfully passes BIST is automatically selected by the hardware as the BSP
and starts executing from the reset vector (F000:FFF0h). A processor that does not perform the
role of BSP is referred to as an application processor (AP).
The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the
machine to boot the operating system. At boot time, the system is in virtual wire mode and the
BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt
controller (PIC) and non-maskable interrupt (NMI)).
As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its
Memory Type Range Registers (MTRRs) to be identical to those of the BSP. All APs execute a
halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that is
a lower-featured processor or that has a lower value returned by the CPUID function, the BSP
switches to the lowest-featured processor in the system.
3.1.8 CPU Thermal Sensors
The CPU temperature will be indirectly measured via the thermal diodes. These are monitored
by the LM93 device. The mBMC configures the LM93 device to monitor these sensors. The
temperatures are available via mBMC IPMI sensors.
3.1.9 Processor Thermal Control Sensor
The Intel Xeon processors generate a signal indicating throttling due to thermal conditions. The
mBMC implements an IPMI sensor that provides the percentage of time a processor has been
throttling over the last 1.46 seconds. Server board management forces a thermal control
condition when reliable system operation requires reduced power consumption.
3.1.10 Processor Thermal Trip Shutdown
If a thermal overload condition exists (thermal trip) an Intel Xeon processor outputs a digital
signal that is monitored by the server board management sub-system. A thermal trip is a critical
condition and indicates that the processor may become damaged if it continues to run. To help
protect the processor, the management controller automatically powers off the system. In
addition it will assert the System Status LED and generate an event in the System Event Log.
3.1.11 Processor IERR
The IERR signal is asserted by the Intel Xeon processor as a result of an internal error. The
mBMC configures the heceta7 device to monitor this signal. When this signal is asserted, the
mBMC generates a processor IERR event.