Filter
Top Products
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
Revision 2.0
4
Table of Contents
1. Introduction ........................................................................................................................17
1.1 Chapter Outline...................................................................................................... 17
1.2 Server Board Use Disclaimer ................................................................................18
2. Server Board Overview......................................................................................................19
2.1 SE7320SP2 SKU Availability.................................................................................19
2.1.1 SE7320SP2 Feature Set .......................................................................................19
2.2 SE7525GP2 SKU Availability ................................................................................22
2.2.1 SE7525GP2 Feature Set ....................................................................................... 22
3. Functional Architecture ..................................................................................................... 25
3.1 Processor Sub-system........................................................................................... 27
3.1.1 Processor VRD ...................................................................................................... 27
3.1.2 Reset Configuration Logic ..................................................................................... 27
3.1.3 Processor Module Presence Detection .................................................................27
3.1.4 GTL2006................................................................................................................27
3.1.5 Common Enabling Kit (CEK) Design Support .......................................................28
3.1.6 Processor Support ................................................................................................. 28
3.1.6.1 Processor Mis-population Detection.....................................................................29
3.1.6.2 Mixed Processor Steppings...................................................................................29
3.1.6.3 Mixed Processor Models.......................................................................................29
3.1.6.4 Mixed Processor Families.....................................................................................29
3.1.6.5 Mixed Processor Cache Sizes ...............................................................................29
3.1.6.6 Jumperless Processor Speed Settings....................................................................30
3.1.6.7 Microcode .............................................................................................................30
3.1.6.8 Processor Cache....................................................................................................30
3.1.6.9 Hyper-Threading Technology...............................................................................30
3.1.6.10 Intel
®
SpeedStep
®
Technology ...........................................................................30
3.1.6.11 EM64T Technology Support ..............................................................................30
3.1.6.12 Execute Disable Bit support................................................................................30
3.1.7 Multiple Processor Initialization .............................................................................31
3.1.8 CPU Thermal Sensors...........................................................................................31
3.1.9 Processor Thermal Control Sensor .......................................................................31
3.1.10 Processor Thermal Trip Shutdown ........................................................................31
3.1.11 Processor IERR ..................................................................................................... 31
3.2 E7320 Chipset ....................................................................................................... 32
3.2.1 Memory Controller Hub (MCH) ..............................................................................32
3.2.1.1 Front Side Bus (FSB)............................................................................................32
3.2.1.2 MCH Memory Sub-System Overview..................................................................32
3.2.1.3 PCI Express*.........................................................................................................33
3.2.1.4 Hub Interface ........................................................................................................33
3.3 E7525 Chipset ....................................................................................................... 33
3.3.1 Memory Controller Hub (MCH) ..............................................................................34
3.3.1.1 Front Side Bus (FSB)............................................................................................34