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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS System BIOS
Revision 2.0
97
Intel will provide the tools and reference code to help OEMs build a user binary. The user binary
must adhere to the following requirements:
• In order to be recognized by the BIOS and protected from runtime memory managers,
the user binary must have an option ROM header (55AA, size).
• The system BIOS performs a scan of the user binary area at predefined points during
POST. Mask bits must be set within the user binary to inform the BIOS if an entry point
exists for a given time during POST.
• The system state must be preserved by the user binary.
• User binary code must be relocatable. It will be located within the first Megabyte. The
user binary code should not make any assumptions about the value of the code segment.
• User binary code will always be executed from RAM and never from flash.
• The code in user binary should not hook critical interrupts, should not re-program the
chipset and should not take any action that affects the correct functioning of the system
BIOS.
The BIOS copies the user binary into system memory before the first scan point. If the user
binary reports that it does not contain runtime code, it is located in conventional memory (0 -
640 KB).
Reporting that the user binary is POSTed has only the advantage that it does not use up limited
option ROM space, and more option ROM space can be used for other devices. If user binary
code is required at run-time, it is copied to the option ROM space. At each scan-point during
POST, the system BIOS determines if the scan-point has a corresponding user binary entry
point to transfer control to.
To determine this, the bitmap at byte 4 of the header is tested against the current mask bit that
has been determined / defined by the scan point. If the bitmap has the appropriate bit set, the
mask is placed in AL and execution is passed to the address computed by (ADR(Byte
5)+5*scan sequence #).
During execution, the user binary may access 11 bytes of Extended BIOS Data Area RAM
(EBDA). The segment of the EBDA can be found at address 40:0e. Offset 18 to offset 21h is
available for the user binary. The BIOS also reserves eight CMOS bits for the user binary.
These bits are in a region of CMOS that does not have a checksum, with default values of zero,
and will always be located in the first bank of CMOS. These bits are contiguous, but are not in a
fixed location. Upon entry into the user binary, DX contains a ‘token’ that points to the reserved
bits.
4.9 Operating System Boot, Sleep, and Wake
4.9.1 Microsoft* Windows* Compatibility
Intel Corporation and Microsoft Corporation co-author design guides for system designers using
Intel
®
processors and Microsoft* operating systems. These documents are updated yearly to
address new requirements and current trends.
PC200x specifications are intended for systems that are designed to work with Windows 2000
and Windows XP class operating systems. The Hardware Design Guide (HDG) for the Windows
XP platform is intended for systems that are designed to work with Windows XP class operating
systems. Each specification classifies the systems further and has requirements based on the
intended usage for that system. For example, a server system that will be used in small