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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
34
3.3.1 Memory Controller Hub (MCH)
The MCH integrates four functions into a single 1077-ball FC-BGA package:
• Front Side Bus
• Memory Controller
• PCI-Express Controller
• Hub Link Interface
3.3.1.1 Front Side Bus (FSB)
The Intel
®
E7525 MCH supports either single or dual processor configurations using Intel Xeon
processors designed for the 800MHz system bus. The MCH supports a base system bus
frequency of 200MHz. The address and request interface is double pumped to 400MHz while
the 64-bit data interface (+ parity) is quad pumped to 800MHz. This provides a matched system
bus address and data bandwidths of 6.4 GB/s.
3.3.1.2 MCH Memory Sub-System Overview
The Intel E7525 MCH provides an integrated memory controller for direct connection to two
channels of registered DDR266, DDR333 or DDR2-400 memory (stacked or unstacked). Peak
theoretical memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/s for
DDR333 technology. For DDR2-400 technology, this increases to 6.4 GB/s.
When both DDR channels are populated and operating, they function in lock-step mode. For the
Intel E7525 MCH, the maximum supported memory size at DDR266, DDR333 or DDR2-400 is
12GB. On the server board SE7525GP2, the maximum supported memory size at DDR266 or
DDR333 is 8GB. DDR2-400 memory is not supported on the server board SE7525GP2.
There are several RASUM (Reliability, Availability, Serviceability, Usability and Manageability)
features built into the Intel E7525 MCH memory interface:
• DIMM sparing allows for one DIMM per channel to be held in reserve and brought on-
line if another DIMM in the channel becomes defective.
• Hardware periodic memory scrubbing, including demand scrub support.
• Retry on uncorrectable memory errors.
• x4 SDDC (Single Device Data Correction) for memory error detection and correction of
any number of bit failures in a single x4 memory device.
3.3.1.3 PCI Express*
The Intel E7525 MCH is part of the first family of Intel chipsets to support the new PCI Express*
high speed serial I/O interface for high I/O bandwidth. The Intel E7525 MCH implementation of
the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev
1.0a. The MCH provides one x16 and one configurable x8 PCI Express interface with a
maximum theoretical bandwidth of 4GB/s. The x8 PCI Express interface may alternatively be
configured (bifurcated) as two independent x4 PCI Express interfaces. On the server board
SE7525GP2, the PCI-Express bandwidth is implemented as one x16 slot for high bandwidth
PCI-Express graphics adapters and one x4 slot for PCI-Express add-in cards.