Filter
Top Products
Chapter 4 Register-Level Programming
© National Instruments Corporation 4-21 PC-DIO-96 User Manual
outp(cnfg,0x84); /* Port B is an output in mode 1. */
outp(cnfg,0x05); /* Set PC2 to enable interrupts from
82C55A. */
outp(ireg1,0x02); /* Set AIRQ1 to enable PPI A, port B
interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */
/* EXAMPLE 5–Set up interrupts for mode 2 output transfers. Enable the
appropriate interrupt bits. */
outp(cnfg,0xC0); /* Mode 2 output. */
outp(cnfg,0x0D); /* Set PC6 to enable interrupts from
82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A
interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */
/* EXAMPLE 6–Set up interrupts for mode 2 input transfers. Enable the
appropriate interrupt bits. */
outp(cnfg,0xD0); /* Mode 2 input. */
outp(cnfg,0x09); /* Set PC4 to enable interrupts from
82C55A. */
outp(ireg1,0x01); /* Set AIRQ0 to enable PPI A, port A
interrupts. */
outp(ireg2,0x04); /* Set INTEN bit. */
}
Programming Considerations for the 8253
A general overview of the 8253 and how it is configured on the PC-DIO-96 are presented as
follows. This section also includes an indepth example of handling interrupts generated by the
8253.
General Information
The 8253 contains three counter/timers, each of which can operate in one of six different modes.
As the PC-DIO-96 is designed, however, only counter 0 and counter 1 are configured for
operation; counter 2 is not connected, nor is it available on the external I/O connector. In
addition, counter 0 and counter 1 are wired to the interrupt circuitry in such a way that only four
of the modes are available for use.
The source for counter 0 is a 2-MHz clock. If counter 0 is used for interrupting the host
computer, configure the counter for rate generation, or mode 2. If counter 1 is used for
interrupting the host computer, counter 0 is used as a frequency scaler which feeds the source
input for counter 1. In this case, configure both counters for rate generation, or mode 2. To
determine the time between pulses generated by counter 0, multiply the load value by 500 nsec
(1/(2 MHz)). To determine the time between pulses generated by counter 1, multiply the load
value by the time between pulses of counter 0. A sample configuration procedure is presented in
the next section.