Filter
Top Products
Register-Level Programming Chapter 4
PC-DIO-96 User Manual 4-28 © National Instruments Corporation
; acknowledge the interrupt
ih_0:
mov ax,seg _DATA
mov ds,ax
mov al,eoi ; Signify end of interrupt
cmp slave_ack,0 ; See if we need to acknowledge slave
je short ih_1 ; Jump if not
out acks,al ; Send slave acknowledge
jmp $+2 ; Delay--wait for data transfer
ih_1:
out ackm,al ; Send master acknowledge
; restore saved registers
pop ds
pop ax
sti
iret
_isr_handler endp
_TEXT ends
end
Interrupt Handling
The INTEN bit of Interrupt Register 2 must be set to enable interrupts from the PC-DIO-96.
This bit must first be cleared to disable unwanted interrupts. After all sources of interrupts have
been disabled or placed in an inactive state, you can set INTEN.
To interrupt the host computer using one of the 82C55A devices, program the selected 82C55A
for the I/O mode desired. In mode 1, set either the INTEA or the INTEB bit to enable interrupts
from port A or port B, respectively. In mode 2, set either INTE1 or INTE2 for interrupts on
output or input transfers, respectively. The INTE1 and INTE2 interrupt outputs are cascaded into
a single interrupt output for port A. After interrupts have been enabled from the 82C55A, set the
appropriate enable bit for the selected 82C55A; for example, if you selected both mode 2
interrupts for PPI C, you would set CIRQ0 in order to interrupt the host computer.
To interrupt the host computer using one of the 8253 counter outputs, program the counter(s) as
described in the preceding section, Interrupt Programming Example for the 8253.
External signals can be used to interrupt the PC-DIO-96 when port A or port B is in mode 0 and
the low nibble of port C is configured for input. If port A is in mode 0, use PC3 to generate an
interrupt; if port B is in mode 0, use PC0 to generate an interrupt. Once you have configured the
selected 82C55A, you must set the corresponding interrupt enable bit in Interrupt Register 1. If
you are using PC3, set xIRQ0; if you are using PC0, set xIRQ1. When the external signal
becomes logic high, an interrupt request occurs. Although the host computer's interrupt-
monitoring circuitry is triggered by the positive-going edge of the interrupt signal, the signal
must remain high until the interrupt routine has been entered and interrupts have been masked
out. Make sure your external interrupt signal meets these qualifications. To disable the external
interrupt, clear the appropriate xIRQy bit or clear the INTEN bit.