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Rev.2.00 Nov 28, 2005 page 139 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram
1/2
DUB1
bit
DQ
T
DQ
T
DQ
T
DQ
T
TQ
TQ
Trigger
Trigger
Trigger
Trigger
Trigger
TQ
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
RESET
NMI
DQ
T
R
U
U
V
V
W
W
1
0
PWCON
1
0
Write signal to
NOTE:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows,
if the INV06 bit is set to "0" (triangular wave modulation mode).
Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.
ICTB2 Register n=1 to 15
INV13
ICTB2 Counter
n=1 to 15
Reload Register
n = 1 to 255
Dead Time
Timer
n = 1 to 255
Dead Time
Timer
n = 1 to 255
Dead Time
Timer
n = 1 to 255
INV00
INV01
INV11
Reload Control Signal for Timer A1
Start Trigger Signal for Timers A1, A2, A4
TA4 Register
Reload
Reload Control
Signal for Timer A4
Reload Control
Signal for Timer A1
Reload Control
Signal for Timer A2
TA41 Register
TA1 Register TA11 Register
Timer A4 Counter
Timer A4
One-Shot
Pulse
Timer A1
One-Shot
Pulse
Timer A2
One-Shot
Pulse
Reload
Timer A1 Counter
(One-Shot Timer Mode)
(One-Shot Timer Mode)
TA2 Register TA21 Register
Reload
Timer A2 Counter
(One-Shot Timer Mode)
When setting the TA4S bit to "0",
signal is set to "0"
When setting the TA1S bit to "0",
signal is set to "0"
When setting the TA2S bit to "0",
signal is set to "0"
INV11
INV10
INV07
INV11
INV11
Timer B2
Timer B2
Timer B2 Underflow
(Timer Mode)
f1 or f2
INV12
INV06
INV06
INV06
Circuit to set Interrupt
Generation Frequency
Timer B2
Interrupt
Request Bit
Value to be written to
INV03 bit
Write signal to INV03 bit
INV05
INV04
INV14
INV02
INV03
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
W-Phase
Output Signal
W-Phase
Output Signal
V-Phase
Output Signal
V-Phase
Output Signal
U-Phase
Output Signal
U-Phase
Output Signal
DUB0
bit
DU1
bit
DU0
bit
U-phase Output
Control Circuit
Transfer Trigger
(1)
Trigger
Trigger
Trigger
Trigger
W-Phase Output
Control Circuit
V-Phase Output
Control Circuit
Three-Phase
Output
Shift Register
(U Phase)
INV00 to INV07: Bits in INVC0 register
INV10 to INV15: Bits in INVC1 register
DUi, DUBi: Bits in IDBi register (i = 0, 1)
TA1S to TA4S: Bits in TABSR register
PWCON: Bits in TB2SC register