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Rev.2.00 Nov 28, 2005 page 311 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 22.10 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
th(BCLK-ALE)
-4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(RD-CS)
th(RD-AD)
BHE
ADi
/DBi
th(RD-DB)
0ns.min
td(AD-ALE)
Read timing
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Address
Data input
40ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
td(BCLK-RD)
th(WR-CS)
Address
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(1.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
25ns.max
tSU(DB-RD)
tac3(RD-DB)
(0.5 ✕ tcyc-10)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
td(AD-WR)
0ns.min
th(ALE-AD)
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
(1.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-15)ns.min
VCC = 5V