Renesas M16C/6NK Network Card User Manual


 
Rev.2.00 Nov 28, 2005 page 173 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface
Under development
This document is under development and its contents are subject to change.
Figure 15.21 TXD and RXD I/O Polarity Inverse
15.1.2.4 Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 15.20 shows serial data logic.
Figure 15.20 Serial Data Logic Switching
15.1.2.5 TXD and RXD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output
data (including the start, stop and parity bits) are inversed. Figure 15.21 shows the TXD and RXD input/output
polarity inverse.
Transfer clock
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
TXDi
(no reverse)
TXDi
(reverse)
SPST D3 D4 D5 D6 D7 PD0 D1 D2
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
(2) When the UiLCH bit = 1 (reverse)
Transfer clock
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
1. This applies to the case where the register bit are set as follows:
CKPOL bit in UiC0 register = 0
(transmit data output at the falling edge of the transfer clock)
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
(1) When the IOPOL bit in the UiMR register = 0 (no reverse)
(2) When the IOPOL bit = 1 (reverse)
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TXDi
(no reverse)
RXDi
(no reverse)
Transfer clock
TXDi
(reverse)
RXDi
(reverse)
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
1. This applies to the case where the register bits are set as follows:
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"