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Rev.2.00 Nov 28, 2005 page 258 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
Table 20.2 Unassigned Pin Handling in Single-chip Mode
Pin Name Connection
Ports P0 to P7, P8_0 to P8_4,
P8_6, P8_7, P9 to P14
(5)
XOUT
(4)
_______
NMI(P8_5)
AVCC
AVSS, VREF, BYTE
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open.
(1) (2) (3)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is
switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeter-
minate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodi-
cally reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
3. When the ports P7_1 and P9_1 are set for output mode, make sure a low-level signal is output from the pins.
The ports P7_1 and P9_1 are N-channel open-drain outputs.
4. With external clock input to XIN pin.
5. The ports P11 to P14 are only in the 128-pin version. When not using all of the P11 to p14 pins may be left
open by setting the PU37 bit in the PUR3 register to “0” (P11 to P14 unusable), without causing any problem.
Table 20.3
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode (Normal-ver. only)
Pin Name Connection
Ports P0 to P7, P8_0 to P8_4,
P8_6, P8_7, P9 to P14
(7)
_______ _______
P4_5/CS1 to P4_7/CS3
________ __________
BHE, ALE, HLDA, XOUT
(5)
,
BCLK
(6)
___________ ________ _______
HOLD, RDY, NMI(P8_5)
AVCC
AVSS, VREF
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open.
(1) (2) (3) (4)
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
_____
corresponding direction bit for CSi (i = 1 to 3) to “0” (input mode) and
_____
the CSi bit in the CSR register to “0” (chip select disabled).
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically
reset in software, for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become indeterminate,
causing the power supply current to increase while they remain set for input ports.
4. When the ports P7_1 and P9_1 are set for output mode, make sure a low-level signal is output from the pins.
The ports P7_1 and P9_1 are N-channel open-drain outputs.
5. With external clock input to XIN pin.
6. If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
7. The ports P11 to P14 are only in the 128-pin version. When not using all of the P11 to p14 pins may be left
open by setting the PU37 bit in the PUR3 register to “0” (P11 to P14 unusable), without causing any problem.