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Rev.2.00 Nov 28, 2005 page 39 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode
Under development
This document is under development and its contents are subject to change.
6.2 Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 6.2 shows the processor mode after hardware reset. Table 6.3 shows the PM01 to PM00 bits set
values and processor modes.
Table 6.2 Processor Mode After Hardware Reset
CNVSS Pin Input Level Processor Mode
VSS Single-chip mode
VCC
(1) (2) (3)
Microprocessor mode
PM01 to PM 00 Bits Processor Mode
00b Single-chip mode
01b
(1)
Memory expansion mode
10b Do not set a value
11b
(1)
Microprocessor mode
NOTES:
1. If the microcomputer is reset in hardware by applying VCC to the CNVSS pin, the internal ROM
cannot be accessed regardless of PM01 to PM00 bits.
2.
_____
The multiplexed bus cannot be assigned to the entire CS space.
3. Not available in T/V-ver.. Do not set a value.
Table 6.3 PM01 to PM00 Bits Set Values and Processor Modes
NOTE:
1. Not available in T/V-ver.. Do not set a value.
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of
whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits cannot
be rewritten to “01b” (memory expansion mode) or “11b” (microprocessor mode)
(1)
at the same time the
PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
NOTE:
1. Not available memory expansion and mocroprocessor modes in T/V-ver..
If the microcomputer is reset in hardware by applying VCC to the CNVSS pin (hardware reset), the internal
ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 6.1 and 6.2 show the processor mode related registers. Figure 6.3 shows the memory map in
_____
single-chip mode. Figures 6.4 to 6.7 show the memory map and CS area in memory expansion mode and
microprocessor mode (Normal-ver. only).