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BASIC TIMER S3C9228/P9228 (Preliminary Spec)
10-4
NOTE: During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
MUX
fXX/4096
DIV
fXX/1024
fXX/128
fXX/16
fXX
Bits 3, 2
Bit 0
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Clear
Bit 1
RESET or STOP
Data Bus
8-Bit Up Counter
(BTCNT, Read-Only)
Start the CPU
(note)
OVF
RESET
R
Figure 10-2. Basic Timer Block Diagram