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S3C9228/P9228 SAM88RCRI INSTRUCTION SET
6-47
SUB — Subtract
SUB dst,src
Operation: dst ¨ dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags: C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign
of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
dst src
opc dst | src 2 4 22 r r
6 23 r lr
opc src dst 3 6 24 R R
6 25 R IR
opc dst src 3 6 26 R IM
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB R1,R2 → R1 = 0FH, R2 = 03H
SUB R1,@R2 → R1 = 08H, R2 = 03H
SUB 01H,02H → Register 01H = 1EH, register 02H = 03H
SUB 01H,@02H → Register 01H = 17H, register 02H = 03H
SUB 01H,#90H → Register 01H = 91H; C, S, and V = "1"
SUB 01H,#65H → Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.