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S3C9228/P9228 I/O PORTS
9-5
Port 0 Interrupt Pending Bits (INTPND1.3-.0)
D6H, Page 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
INTPND1 bit configuration settings:
0
1
P0.3
(INT)
Interrupt is pending (when read)
No interrupt pending (when read), clear pending bit (when write)
P0.2
(INT)
P0.1
(INT)
P0.0
(INT)
P1.3
(INT)
P1.2
(INT)
P1.1
(INT)
P1.0
(INT)
Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
Port 0 Interrupt Edge Selection Register (P0EDGE)
EEH, Page 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
P0EDGE bit configuration settings:
0
1
P0.3
(INT)
Rising edge detection
Falling edge detection
P0.2
(INT)
P0.1
(INT)
P0.0
(INT)
Not used
Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
Port 0 Pull-up Control Register (P0PUR)
ECH, Page 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
P0PUR bit configuration settings:
0
1
Enable pull-up resistor
Disable pull-up resistor
Not used P0.3 P0.2 P0.1 P0.0
Figure 9-6. Port 0 Pull-up Control Register (P0PUR)