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S3C9228/P9228 TIMER 1
11-5
TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using
register addressing mode.
A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency
of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.3.
A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency
of fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation
by writing a "1" to TBCON.3.
To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2
(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3
(TBCON.3) and INTPND2.0 (INTPND2.1), which cleared counter and interrupt pending bit. To detect an interrupt
pending condition when TAINT and TBINT is disabled, the application program polls pending bit, INTPND2.0 and
INTPND2.1. When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When
the TAINT and TBINT sub-routine has been serviced, the pending condition must be cleared by software by
writing a "0" to the timer A and B interrupt pending bit, INTPND2.0 and INTPND2.1.
Timer A Control Register (TACON)
E4H, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Timer A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used
Timer A counter enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer A counter clear bit:
0 = No affect
1 = Clear the timer A counter (when write)
One 16-bit timer or Two 8-bit
timers mode:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer A clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available
Figure 11-3. Timer A Control Register (TACON)