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S3C9228/P9228 I/O PORTS
9-3
PORT 0
Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or
reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pull-
up), as outputs (push-pull or open-drain) or you can be configured the following functions.
— Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT
— High-nibble pins (P0.4-P0.5): push-pull output ports (only 44-QFP package)
Port 0 Control register (P0CON)
Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to “00H”, configuring
pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and
enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using
the port 0 control register must also be enabled in the associated peripheral module.
Port 0 Pull-up Resistor Control Register (P0PUR)
Using the port 0 pull-up resistor control register, P0PUR (ECH, page 0), you can configure pull-up resistors to
individual port 0 pins.
Port 0 Interrupt Enable, Pending, and Edge Selection Registers (P0INT, INTPND1.3-.0, P0EDGE)
To process external interrupts at the port 0 pins, three additional control registers are provided: the port 0
interrupt enable register P0INT (EDH, page 0), the port 0 interrupt pending bits INTPND1.3-.0 (D6H, page 0), and
the port 0 interrupt edge selection register P0EDGE (EEH, page 0).
The port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the INTPND1.3-.0 register at regular intervals.
When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the
CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.