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Major Chips Description 2-15
Table 2-2 82371AB Pin Descriptions
Name Type Description
XOE#/
GPO23
O
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output
enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data
bus, SD[7:0]. XOE# is asserted anytime a PIIX4 supported X-Bus device is
decoded, and the devices decode is enabled in the X-Bus Chip Select Enable
Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B
(PCCS0#) and Device Resource C (PCCS1#). XOE# is asserted from the falling
edge of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master
and ISA master-initiated cycles. XOE# is negated from the rising edge of the ISA
command signals for PCI Master initiated cycles and the SA[16:0] and LA[23:17]
address for ISA master-initiated cycles. XOE# is not generated during any access
to an X-Bus peripheral in which its decode space has been disabled. If an X-Bus
not used, then this signal can be programmed to be a general purpose output.
During Reset: High After Reset: High During POS: High/GPO
DMA SIGNALS
DACK[0,1,2,3]
#
DACK[5,6,7]#
O
DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA
service has been granted by PIIX4 or that a 16-bit master has been granted the
bus. The active level (high or low) is programmed via the DMA Command
Register. These lines should be used to decode the DMA slave device with the
IOR# or IOW# line to indicate selection. If used to signal acceptance of a bus
master request, this signal indicates when it is legal to assert MASTER#. If the
DREQ goes inactive prior to DACK# being asserted, the DACK# signal will not be
asserted.
During Reset: High After Reset: High During POS: High
DREQ[0,1,2,3]
DREQ[5,6,7]
I
DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4’s
DMA controller or for a 16-bit master to gain control of the ISA expansion bus.
The active level (high or low) is programmed via the DMA Command Register. All
inactive to active edges of DREQ are assumed to be asynchronous. The request
must remain active until the appropriate DACKx# signal is asserted.
REQ[A:C]#/
GPI[2:4]
I
PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI
protocol. They are used by a PCI agent to request DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the
PCI DMA
section. If
the PC/PCI request is not needed, these pins can be used as general-purpose
inputs.
GNT[A:C]#/
GPO[9:11]
O
PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI
protocol. They are used by a PIIX4 to acknowledge DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the
PCI DMA
section. If
the PC/PCI request is not needed, these pins can be used as general-purpose
outputs.
During Reset: High After Reset: High During POS: High/GPO
TC O
TERMINAL COUNT. PIIX4 asserts TC to DMA slaves as a terminal count
indicator. PIIX4 asserts TC after a new address has been output, if the byte count
expires with that transfer. TC remains asserted until AEN is negated, unless AEN
is negated during an autoinitialization. TC is negated before AEN is negated
during an autoinitialization.
During Reset: Low After Reset: Low During POS: Low