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2-20 Service Guide
Table 2-2 82371AB Pin Descriptions
Name Type Description
PDDACK# O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that
a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data
transfer cycle. This signal is used in conjunction with the PCI bus master IDE
function. It is not associated with any AT compatible DMA channel. If the IDE
signals are configured for Primary and Secondary, this signal is connected to the
corresponding signal on the Primary IDE connector. If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the
Primary Master connector.
During Reset: High After Reset: High During POS: High
PDDREQ I
PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE
device DMARQ signal. It is asserted by the IDE device to request a data transfer,
and used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel. If the IDE signals are configured for
Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector. If the IDE signals are configured for Primary Master
and Primary Slave, this signal is used for the Primary Master connector.
PDIOR# O
PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device
that it may drive data onto the PDD[15:0] lines. Data is latched by PIIX4 on the
negation edge of PDIOR#. The IDE device is selected either by the ATA register
file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA
slave arbitration signals (PDDACK#). In an Ultra DMA/33 read cycle, this signal
is used as DMARDY# which is negated by the PIIX4 to pause Ultra DMA/33
transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE
signal, with the drive latching data on rising and falling edges of STROBE. If the
IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector. If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the
Primary Master connector.
During Reset: High After Reset: High During POS: High
PDIOW# O
PRIMARY DISK IO WRITE. In normal IDE mode, this is the command to the IDE
device that it may latch data from the PDD[15:0] lines. Data is latched by the IDE
device on the negation edge of PDIOW#. The IDE device is selected either by
the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or
the IDE DMA slave arbitration signals (PDDACK#). For Ultra DMA/33 mode, this
signal is used as the STOP signal, which is used to terminate an Ultra DMA/33
transaction. If the IDE signals are configured for Primary and Secondary, this
signal is connected to the corresponding signal on the Primary IDE connector. If
the IDE signals are configured for Primary Master and Primary Slave, this signal
is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High-Z
PIORDY I
PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is
directly driven by the corresponding IDE device IORDY signal. In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data
on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this signal
is used as the DMARDY# signal which is negated by the drive to pause Ultra
DMA/33 transfers. If the IDE signals are configured for Primary and Secondary,
this signal is connected to the corresponding signal on the Primary IDE
connector. If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector. This is a Schmitt
triggered input.