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Version 0.3, 4 December, 2000 DCSE: PowerEdge 1550 Self-Study
Dell Page 65
• Flexibility to use a BIOS with minimal MP-specific support.
• An optional MP configuration table to communicate configuration
information to an MP operating system.
• Incorporation of ISA and other industry standard buses, such as EISA,
MCA, VL and PCI buses in MP-compliant systems.
• Requirements that make secondary cache and memory bus implementation
transparent to software.
SMBIOS 2.3.1
The Desktop Management Interface (DMI) is a method of managing
computers in an enterprise. The main component of DMI is the
Management Information Format Database, or MIF. This database
contains all the information about the computing system and its
components. Using DMI, a system administrator can obtain the types,
capabilities, operational status, installation date, and other information
about the system components.
The Desktop Management Interface Specification and its companion
MASTER.MIF define “manageable attributes that are expected to be
supported by DMI-enabled computer systems”. Many of these attributes
have no standard interface to the management software, but are known by
the system BIOS. The System Management BIOS Reference Specification
provides that interface via data structures through which the system
attributes are reported.
Processor
The processor has 256-KB Level 2 cache running at the internal frequency
and sits in a socket 370 FC-PGA (Flip Chip Pin Grid Array) socket. The
term Flip Chip refers to the location of the processor chip itself in relation
to the package. On previous socketed processors the chip was on the
underside of the package (the side facing the socket). On the FC-PGA
package the chip sits on top of the package (the side with the heat sink).
This is intended to more efficiently conduct the heat away from the chip.
On the "Coppermine" processor the Floating Point Unit (FPU) can pass
data to the processor 256 bytes at a time. This is a four-fold increase over
the previous "Katmai" processor. Changing from 4-way set associative
cache architecture to 8-way set associative also increased L2 Cache
efficiency. The buffers were increased which further increased efficiency.
Onboard SCSI-3
The AIC-7899 supports the Ultra160/m SCSI-3 specification providing for
up to 160MB/s maximum theoretical throughput per channel. The system
board will make use of both channels providing two (2) LVD (Low