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Version 1.4 2-1
2
System Overview
In the realm of multiprocessor architectures, there are several conceptual models for tying together
computing elements, and there are a variety of interconnection schemes and details of
implementation. Figure 2-1 shows the general structure of a design based on the MP specification.
The MP specification’s model of multiprocessor systems incorporates a tightly-coupled, shared-
memory architecture with a distributed interprocessor and I/O interrupt capability. It is fully
symmetric; that is, all processors are functionally identical and of equal status, and each processor
can communicate with every other processor. There is no hierarchy, no master-slave relationship,
no geometry that limits communication only to “neighboring” processors. The model is symmetric
in two important respects:
• Memory symmetry. Memory is symmetric when all processors share the same memory space
and access that space by the same addresses. Memory symmetry offers a very important
feature—the ability for all processors to execute a single copy of the operating system. Any
existing system and application software will execute the same, regardless of the number of
processors installed in a system.
• I/O symmetry. I/O is symmetric when all processors share access to the same I/O subsystem
(including I/O ports and interrupt controllers) and any processor can receive interrupts from
any source. Some multiprocessor systems that have symmetric access to memory are actually
asymmetric with regard to I/O interrupts, because they dedicate one processor to interrupt
functions. I/O symmetry helps eliminate the potential of an I/O bottleneck, thereby increasing
system scalability.
With both memory and I/O symmetry, a system that complies with the MP specification can
achieve hardware scalability as well as support software standardization. Based on this kind of
scalable architecture, systems developers can produce systems that span a wide range of price and
performance, and that all execute the same binaries.