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Default Configurations
Version 1.4 5-5
A
B
C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
IRQ1
0
1
2
3
4
5
6
7
I/O
APIC
MASTER
8259A PIC
SLAVE
8259A PIC
IRQ8# INT8
14
15
14
15
8254 TIMER
9
10
11
9
10
11
3
4
5
6
7
3
4
5
6
7
INTR
NMI
REG.
MARK
LOCAL
APIC
LOCAL
APIC
APICEN
PENTIUM (735\90, 815\100)
CPU2
BSP AP
INIT
SMI#
ICC BUS
INTR/LINT0
NMI/LINT1
INIT
SMI#
IMCR
E0
IRQ3-7,
9-12,14,15
IRQ13
EISA DMA CHAINING
FERR#
IGNNE#
FERR
SAMPLING
FROM BSP
EDGE/LEVEL TRIGGER
POLARITY CONTROL
12
ABFULL
(PS/2 MOUSE)
LITM3-7,
9-12,14,15
LITMx
IRQx
ABFULL
SAMPLING
12
13
PIRQ
MAPPING
PIRQ0-3
3-7,9-11,14,15
D
PENTIIUM (735\90, 815\100)
CPU1
APICEN
SHADED AREAS:
A,B: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS
B,C: EISA BUS SPECIFIC
D: PCI BUS SPECIFIC
Figure 5-2. Default Configuration for Integrated APIC
Two local interrupt input pins, LINT0 and LINT1, are shared with the INTR and NMI pins,
respectively. The LINT0, LINT1, SMI# and INIT signals are switched by APICEN, and they