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MultiProcessor Specification
B-6 Version 1.4
of an INIT IPI used to shut down an AP. As a result, the operating system must ensure that any
required state information is captured and that caches are flushed as necessary before sending the
INIT IPI.
In order to do a complete system shutdown, followed by a warm restart if necessary, the operating
system should return the system to a state similar to that at power-on. This includes disabling the
Local APIC interrupts (LINT0/LINT1/Local APIC Timer/Error interrupt) on all processors,
disabling the Local APIC on all APs and disabling all interrupts at all the I/O APICs in the system.
The operating system can use an IPI or an NMI to signal to all APs for per-processor shutdown
handling. The operating system may then set the CMOS shutdown code to 0Ah and perform a
keyboard controller reset.
B.6 Other IPI Applications
The operating system may use IPIs for other run-time duties, such as handling the various
processor caches.
B.6.1 Handling Cache Flush
The MP specification requires that hardware maintain cache coherency. Cache flushing by the
operating system should not be required under normal circumstances. The only need for cache
flushing by the operating system is prior to powering down a processor.
Should a system-wide cache flush be necessary, the operating system should use the broadcast IPI
mechanism to request that each of the processors write back and invalidate its own cache
subsystem and then synchronize upon the completion of that activity.
B.6.2 Handling TLB Invalidation
The operating system should use the IPI mechanism to request that each of the processors
invalidate its TLBs. The operating system may use a broadcast IPI for this purpose. The BSP and
APs should synchronize the completion of their actions either via memory-based semaphores or via
targeted return IPIs. The actual IPI vector is operating system dependent.
B.6.3 Handling PTE Invalidation
The operating system should use the IPI mechanism to request that each processor invalidate a
specific page-table entry (PTE) if it is cached in that processor’s TLBs. The operating system may
use a broadcast IPI for this purpose. The BSP and APs should synchronize the completion of their
actions either via memory-based semaphores or via targeted return IPIs. The actual IPI vector is
operating system dependent.
B.7 Spurious APIC Interrupts
For the 8259, there is a time window in which a spurious interrupt may be misinterpreted as a
genuine interrupt. For example, if an interrupt goes inactive just after the first INTA cycle but
before the second INTA cycle, the 8259 will also signal this spurious interrupt as a genuine