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MultiProcessor Specification
2-4 Version 1.4
The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to
interrupt any other processor or set of processors. There are several types of IPIs. Among them,
the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown.
Each local APIC has a Local Unit ID Register and each I/O APIC has an I/O Unit ID Register.
The ID serves as a physical name for each APIC unit. It is used by software to specify destination
information for I/O interrupts and interprocessor interrupts, and is also used internally for accessing
the ICC bus.
Due to the distributed architecture, the APIC local and I/O units can be implemented in either a
single chip, such as Intel’s 82489DX interrupt controller, or they can be integrated with other parts
of the system’s components. For example, the local APIC may be integrated with the CPU chip,
such as Intel’s Pentium processors (735\90, 815\100), and the I/O APIC may be integrated with the
I/O chipset, such as Intel’s 82430 PCI-EISA bridge chipset.
2.1.3 System Memory
A system that complies with the MP specification uses the standard AT memory architecture. All
memory is allocated for system memory with the exception of addresses 0A_0000h through
0F_FFFFh and 0FFFE_0000h through 0FFFF_FFFFh, which are reserved for I/O devices and the
BIOS.
Compared to a uniprocessor system, a symmetric multiprocessor system imposes a high demand
for memory bus bandwidth. The demand is proportional to the number of processors on the
memory bus. To reduce memory bus bandwidth limitations, an implementation of this
specification should use a secondary cache that has high-performance features, such as a write-back
update policy and a snooping cache-consistency protocol. A secondary cache can push the
scalability limit upward by reducing bus traffic and increasing bus bandwidth.
While both secondary caches and memory bus controllers are critical components for high
performance in a symmetric multiprocessor system, this specification does not detail their
implementation, requiring only that they be totally software transparent.
2.1.4 I/O Expansion Bus
The MP specification provides a multiprocessor extension to the industry-standard PC/AT
platform. The term “industry-standard PC/AT platform” here refers to the software-visible
components of the PC/AT. The standard does not designate a specific bus architecture. All
industry-standard buses, such as ISA, EISA, MCA, VL, and PCI, can be incorporated in the
design. Systems developers can implement one or more bus types in their designs, depending on
the systems’ I/O performance or capacity requirements.