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MultiProcessor Specification
A-2 Version 1.4
A.2 Controlling the Application Processors
Provision must be made to prevent all processors from executing the BIOS after a power-on
RESET. System developers may choose to do this by the hardware alone or by cooperation
between hardware and the BIOS. In the latter case, the BIOS may be used for selecting the BSP
and placing all APs to sleep after POST. The BIOS may use the APIC ID as a means by which to
identify each processor and select the proper code sequence to execute. Only the selected BSP
continues to load the operating system after the POST routine.
A.3 Programming the APIC for Virtual Wire Mode
The APICs do not require BIOS programming if the default interrupt mode at start-up is PIC
Mode. Special programming is needed only if the startup interrupt mode is Virtual Wire Mode.
Because Virtual Wire Mode must run all existing uniprocessor software, the system BIOS must
initialize and enable the BSP’s APIC first. The local unit must be programmed to function as a
“virtual wire,” which delivers the CPU interrupt from the 8259A-equivalent PIC to the BSP via its
local APIC.
The External Interrupt (ExtINT) delivery mode must be used so that the APICs and 8259A-
equivalent PICs can function together in the same system. For interrupts that are programmed for
ExtINT delivery mode, there is no need to issue an EOI to the APIC; only the 8259A PIC requires
an EOI as usual. Also, because the 8259A delivers the vector to the processor for ExtINT delivery
mode, the interrupt vector in the APIC’s redirection table is ignored.
To program the APIC to Virtual Wire Mode, the system BIOS must program the APIC to enable
the LINT0 of the BSP’s local APIC for edge-triggered ExtINT delivery mode, and LINT1 for
level-triggered NMI delivery mode. There is no need to program the I/O APIC if it is not used in
Virtual Wire Mode.
Example A-1 is an example of programming the LINTIN0 and LINTIN1 to support Virtual Wire
Mode.