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MultiProcessor Specification
2-2 Version 1.4
HIGH-BANDWIDTH MEMORY BUS
APIC
ADVANCED PROGRAMMABLE
INTERRUPT CONTROLLER
ICC INTERRUPT CONTROLLER
COMMUNICATIONS
CPU CPU CPU
SHARED
MEMORY
MODULE
GRAPHICS
FRAME
BUFFER
I/O
INTERFACE
APIC
I/O
INTERFACE
APIC
ICC BUS
I/O EXPANSION BUSI/O EXPANSION BUS
Figure 2-1. Multiprocessor System Architecture
2.1 Hardware Overview
The MP specification defines a system architecture based on the following hardware components:
• One or more processors that are Intel architecture instruction set compatible, such as the CPUs
in the Intel486 and the Pentium processor family.
• One or more APICs, such as the Intel 82489DX Advanced Programmable Interrupt Controller
or the integrated APIC on the Pentium 735\90 and 815\100 processors.
• Software-transparent cache and shared memory subsystem.
• Software-visible components of the PC/AT platform.
2.1.1 System Processors
To maintain compatibility with existing PC/AT software products, this specification is based on
the Intel486 and the Pentium processor family. To achieve a minimum level of MP system
performance, two or more processors that are Intel architecture instruction set compatible are
required.
Figure 2-2 gives a different point of view of a compliant system, showing the configuration of the
APICs with respect to the CPUs. While all processors in a compliant system are functionally
identical, this specification classifies them into two types: the bootstrap processor (BSP) and the
application processors (AP). Which processor is the BSP is determined by the hardware or by the
hardware in conjunction with the BIOS. This differentiation is for convenience and is in effect