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MultiProcessor Specification
B-4 Version 1.4
A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal
operating conditions. If the IPI is not successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by writing the lower 32-bit double
word of the ICR. This “time-out” mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of an instruction or time-stamp
counter spin loop.
Optionally, the operating system can make use of the information provided by the integrated APIC
error register. Integrated local APIC units on Intel Architecture processors provide an APIC error
register that indicates the reason for non-delivery of an APIC message. Reasons for non-delivery
include SEND_ACCEPT and RECEIVE_ACCEPT errors that are generated when no processor
responds to a message on the APIC bus. An example of this type of failure includes sending a
STARTUP IPI to a destination APIC ID for a non-existent processor. Other errors are usually
indicative of hardware problems and include SEND and RECEIVE CHECKSUM errors.
The operating system is responsible for determining whether the IPI was received by the targeted
AP and executed successfully. For example, the operating system can define a status flag for each
processor. After being awakened, a processor sets its status flag, indicating to the operating system
that it is present and running. If the status flag does not change value after a certain time, the
operating system should treat the processor as not present or not functional.
The following two sections describe specifics relating to the use of INIT and STARTUP IPIs that
can be used to guide the implementation of the universal algorithm presented here.
B.4.1 USING INIT IPI
INIT IPIs can be used with systems based on the 82489DX APIC, or on systems that are based on
multiple Pentium (735/90, 815/100) processors. INIT IPI is an Interprocessor Interrupt with trigger
mode set to level and delivery mode set to “101” (bits 8 to 10 of the ICR). INIT IPIs should
always be programmed as level triggered; the operating system must perform two writes to the ICR
to assert and then deassert this delivery mode.
An INIT IPI is an IPI that has its delivery mode set to RESET. Upon receiving an INIT IPI, a local
APIC causes an INIT at its processor. The processor resets its state, except that caches, floating
point unit, and write buffers are not cleared. Then the processor starts executing from a fixed
location, which is the reset vector location. To cause the processor to jump to a different location,
the INIT IPI must be used as part of a warm-reset.
The warm reset is a feature of every standard PC/AT BIOS. It allows the INIT signal to be
asserted without actually causing the processor to run through its entire BIOS initialization
procedure (POST). This feature is used, for example, to return an 80286 processor to Real Mode.
The key components of warm reset are the following:
• Shutdown code. One of the first actions of the BIOS POST procedure is to read the shutdown
code from location 0Fh of the CMOS RAM. This code can have any of several values that
indicate the reason that an INIT was performed. A value of 0Ah indicates a warm reset.
• Warm-reset vector. When POST finds a shutdown code of 0Ah, it executes an indirect jump
via the warm-reset vector, which is a doubleword pointer in system RAM location 40:67h.