Filter
Top Products
Version 1.4 D-1
D
Multiple I/O APIC
Multiple PCI Bus Systems
The information in this specification describes the majority of multiprocessor systems. This
appendix provides clarifications for implementors who are considering designs with more than one
I/O APIC. In particular, a number of proposed systems will incorporate multiple I/O APICs in
order to support multiple PCI buses. This appendix provides guidance for implementors who wish
to be sure that their designs comply with this specification.
D.1 Interrupt Routing with Multiple APICs
Two basic approaches to routing interrupts can be used when the system has more than one I/O
APIC:
• The fixed routing scheme uses the same routing in both PIC or Virtual Wire Mode and
symmetric I/O mode.
• The variable approach changes the routing when switching to symmetric I/O mode.
This section applies when a PCI interrupt is connected both to an I/O APIC input of its own and to
the I/O APIC input of the EISA/ISA IRQ to which the interrupt is routed when in PIC or Virtual
Wire Mode. This double routing is typically used to preserve PC AT compatibility at system start-
up, allowing a system to boot from a disk connected to a PCI controller on a second PCI bus, for
example. To prevent double delivery of this PCI interrupt once the system switches to symmetric
I/O mode for an MP operating system, the duplicate routing must either be turned off or concealed
from the operating system. If a PCI interrupt is only connected via an EISA/ISA IRQ, the
EISA/ISA entry in the MP configuration table is sufficient to describe the routing.
The variable routing method described below is preferred since it is more flexible and offers best
use of available system resources. Fixed routing is described here for compatibility with existing
systems that do not implement a variable routing strategy.
D.1.1 Variable Interrupt Routing
In systems with variable interrupt routing, all PCI interrupts map to EISA/ISA IRQs when in PIC
or Virtual Wire Mode. When switched to symmetric I/O mode, the system disables this routing
and delivers the PCI interrupt through I/O APIC inputs different from those used by the EISA/ISA
IRQs.
If IMCR is implemented, the hardware design can use this bit to enable/disable the routing of the
PCI interrupts to EISA/ISA IRQs. On systems with IMCR, this operation might be the only one
that is required of the operating system when switching to symmetric I/O mode, other than the
actual programming of the I/O and Local APICs.