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Hardware Specification
Version 1.4 3-5
operations over its internal shared memory bus, if it is AT compatible. Operating system and
software developers must ensure
that data is aligned if locked access is required, because lock
operations on misaligned data are not guaranteed to work on all platforms.
3.5 Posted Memory Write
When controlling I/O devices, it is important that memory and I/O operations be carried out in the
order programmed. Intel-compatible processors do not buffer I/O writes; thus, strict ordering
among I/O operations is enforced by the processors.
To optimize memory performance, processors and chipsets often implement write buffers and
writeback caches. Intel-compatible processors guarantee processor ordering on all internal cache
and write buffer accesses. However, chipsets must also guarantee processor ordering on all
external memory accesses.
For systems based on the integrated APIC, posting of memory writes may result in spurious
interrupts for memory-mapped I/O devices using level-triggered interrupts. I/O device drivers
must serialize instructions to ensure that the device interrupt clear command reaches the device
before the EOI command reaches the APIC and handles the spurious interrupt in case one occurs.
3.6 Multiprocessor Interrupt Control
In an MP-compliant system, interrupts are controlled through the APIC. The following sections
describe the APIC architecture and the three interrupt modes allowed in an MP-compliant system.
3.6.1 APIC Architecture
The Intel Advanced Programmable Interrupt Controller (APIC) is based on a distributed
architecture. Interrupt control functions are distributed between two basic functional units: the
local unit and the I/O unit. The local and I/O units communicate through a bus called the ICC bus.
The I/O unit senses an interrupt input, addresses it to a local unit, and sends it over the ICC bus.
The local unit that is addressed accepts the message sent by the I/O unit.
In an MP-compliant system, one local APIC per CPU is required. Depending on the total number
of interrupt lines in an MP system, one or more I/O APICs may be used. The bus interrupt line
assignments can be implementation-specific and can be defined by the MP configuration table
described in Chapter 4.
The Intel 82489DX APIC is a “discrete APIC” implementation. The programming interface of the
82489DX APIC units serves as the base of the MP specification. Each APIC has a version register
that contains the version number of a specific APIC implementation. The version register of the
82489DX family has a version number of “0x,” where x is a four-bit hexadecimal number. Version
number “1x” refers to Pentium processors with integrated APICs, such as the Pentium 735\90 and
815\100 processors, and x is a four-bit hexadecimal number.
The integrated APIC maintains the same programming interface as the 82489DX APIC. Table 3-2
describes the features specific to the integrated APIC.