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Hardware Specification
Version 1.4 3-11
3.6.2.3 Symmetric I/O Mode
Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O
APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt
lines are either masked or work together with the I/O APIC in a mixed mode. See Figure 3-5 for
an overview of Symmetric I/O Mode.
LINTIN0 LINTIN1
NMI
NMI
INTR
CPU 1
LINTIN0 LINTIN1 LINTIN0 LINTIN1
NMI INTR
CPU 2
NMI INTR
CPU 3
REG.
MARK
BSP AP1 AP2
LOCAL
APIC
1
LOCAL
APIC
2
LOCAL
APIC
3
RESET
LINTIN0
LINTIN1
ICC BUS
INTR
I/O
APIC
8259A-
EQUIVALENT
PICS
INTERRUPT INPUTS
SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.
Figure 3-5. Symmetric I/O Mode
The APIC I/O unit has general-purpose interrupt inputs that can be individually programmed to
different operating modes. The I/O APIC interrupt line assignments are system implementation
specific. Refer to Chapter 4 for custom implementations and to Chapter 5 for default
configurations.
The hardware must support a mode of operation
in which the system can switch easily to
Symmetric I/O mode from PIC or Virtual Wire mode. When the operating system is ready to
switch to MP operation, it writes a 01H to the IMCR register, if that register is implemented, and
enables I/O APIC Redirection Table entries. The hardware must not require any other action on the
part of software to make the transition to Symmetric I/O mode.