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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE
5-5
Table 5-1. Interrupt Vectors
Vector Address Interrupt Source Request Reset/Clear
Decimal
Value
Hex
Value
Interrupt
Level
Priority in
Level
H/W S/W
256 100H Basic timer overflow Reset
− √
242 F2H Timer B match IRQ0 1
√
240 F0H Timer 1/A match 0
√
244 F4H SIO interrupt IRQ1
−
√
246 F6H Watch timer overflow IRQ2
−
√
224 E0H P0.0 external interrupt IRQ3
−
√
226 E2H P0.1 external interrupt IRQ4
−
√
228 E4H P0.2 external interrupt IRQ5
−
√
230 E6H P1.3 external interrupt IRQ6
−
√
238 EEH P1.7 external interrupt IRQ7 3
√
236 ECH P1.6 external interrupt 2
√
234 EAH P1.5 external interrupt 1
√
232 E8H P1.4 external interrupt 0
√
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.