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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
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FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Revision History
Revision No.
0.2
1.0
1.1
History
1. Corrected errata.
2. Chapter 2.1 Detailed Product Description revised.
3. Chapter 2.2 Definitions revised.
4. Chapter 2.8.3 Device ID Register F001h(R) revised.
5. Chapter 2.8.8 Technology Register F006h(R) revised.
6. Chapter 2.8.10 Start Address2 Register F101h(R/W) revised.
7. Chapter 2.8.16 Start Address8 Register F107h(R/W) revised.
8. Chapter 2.8.18 Command Register F220h(R/W) revised.
9. Chapter 2.8.22 Interrupt Status Register F241h(R/W) revised.
10. Chapter 3.1 Command Based Operation revised.
11. Chapter 3.3 Reset Mode Operation revised.
12. Chapter 3.4.3 NAND Array Write Protection States revised.
13. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State revised.
14. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State
revised.
15. Chapter 3.4.4 NAND Flash Array Write Protection State Diagram
revised.
16. Chapter 3.6.2 LSB Page Recovery Read revised.
17. Chapter 3.7.2 Synchronous Read Mode Operation revised.
18. Chapter 3.7.2.1 Continuous Linear Burst Read Operation revised.
19. Chapter 3.9 Program Operation revised.
20. Chapter 3.9.1 Cache Program Operation revised.
21. Chapter 3.9.2 Interleave Cache Program Operation revised.
22. Chapter 3.11.1 Block Erase Operation revised.
23. Chapter 3.11.2 Erase Suspend / Erase Resume Operation revised.
24. Chapter 3.12 Partition Information (PI) Block(SLC Only) revised.
25. Chapter 3.12.1 PI Block Boundary Information setting revised.
26. Chapter 3.12.1.1 PI Block Access mode entry revised.
27. Chapter 3.12.1.2 PI Block Erase revised.
28. Chapter 3.12.1.3 PI Block Program Operation revised.
29. Chapter 3.12.1.4 PI Update revised.
30. Chapter 3.13 OTP Operation (SLC only) revised.
31. Chapter 3.13.1 OTP Block Load Operation revised.
32. Chapter 3.16.2 Invalid Block Replacement Operation revised.
33. Chapter 5.5 AC Characteristics for Asynchronous Read revised.
34. Chapter 6.3 Asynchronous Read(VA Transition Before AVD Low) tOEH
removed.
35. Chapter 6.4 Asynchronous Read(VA Transition After AVD Low) tOEH
removed.
36. Chapter 7.4 DDP and QDP Description inserted.
1. New Format(font size, color etc.)
2. Corrected errata.
3. Added a comment(Chapter 3.11.1 & 3.12.1.2 & 3.12.1.3 & 3.12.1.4)
4. Chapter 2.8.17 Start Buffer Register F200h (R/W) revised.
5. Chapter 3.1.2 Load Data Into Buffer Command revised.
6. Chapter 3.12.2 PI Block Load Operation revised.
7. Chapter 4.3 DC Characteristics revised.
1. Chapter 3.6.2 LSB Page Recovery read flow chart revised.
2. Chapter 3.9.1 Cache Program Operation revised.
3. Chapter 3.13.1 OTP Block Read Operation Flow Chart revised.
4. Chapter 3.13.2 OTP Block Program Operation Flow Chart revised.
5. Chapter 3.13.3 OTP Block Lock Operation Flow Chart revised.
6. Chapter 3.13.4 1st Block OTP Lock Operation revised.
7. Chapter 3.13.5 OTP and 1st Block OTP Lock Operation Flow Chart
revised.
Draft Date
Oct. 30, 2007
Feb. 04, 2008
Aug. 07, 2008
Remark
Preliminary
Final
Final