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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
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FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
OTP Block Program Operation Flow Chart
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
3) Data input could be done anywhere between "Start" and "Write Program Command".
4) FBA must be 0000.
5) FSA must be 00 within program operation.
6) BSA must be 1000 and BSC must be 000.
Select DataRAM for DDP
Add: F101h DQ=DBS*
Write ‘DFS*, FBA’ of Flash
1)
Add: F100h DQ=DFS*, FBA
Start
Data Input
Write ‘OTP Access’ Command
Add: F220h DQ=0065h
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
5)
Write ‘BSA, BSC’ of DataRAM
Add: F200h DQ=0800h
6)
Write Data into DataRAM
3)
Add: DP DQ=Data-in
OTP Programming completed
Write Program command
DQ=0080h
Completed?
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
NO
Add: F220h
Wait for INT register
Add: F241h DQ[15]=INT
Write 0 to interrupt register
2)
Add: F241h DQ=0000h
low to high transition
Do Cold/Warm/Hot
OTP Exit
Automatically
checked
Update Controller
Add: F240h
Status Register
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
OTP Exit
Automatically
OTPL=0?
YES
NO
updated
Read Controller
Status Register
Add: F240h DQ[10]=1(Error)
DQ[14]=1(Lock), DQ[10]=1(Error)
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
4)
Read Controller
Status Register
Add: F240h DQ[10]=0(Pass)
/NAND Flash Core reset
Do Cold/Warm/Hot
/NAND Flash Core reset
Write 0 to interrupt register
2)
Add: F241h DQ=0000h
* DBS, DFS is for DDP